VLSI Projects

Design and Implementation of a Field Programmable CRC Circuit Architecture---IEEE 2009.
	Exploiting Memory Soft Redundancy for Joint Improvement of Error Tolerance and Access Efficiency---IEEE 2009.
	Soft-Error Tolerance and Mitigation in Asynchronous Burst-Mode Circuits---IEEE 2009.
	Design of Network-on-Chip Architectures with a Genetic Algorithm-Based Technique---IEEE 2009.
	Efficient On-Chip Crosstalk Avoidance CODEC Design---IEEE 2009.
	Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits---IEEE 2009.
	Fault Secure Encoder and Decoder for Memory Applications---IEEE 2007.
	A Fast VLSI Design of SMS4 Cipher Based on Twisted BDD S-Box Architecture---IEEE 2009.
	A Full-Adder-Based Methodology for the Design of Scaling Operation in Residue Number System---IEEE 2008.
	A Generalization of a Fast RNS Conversion for a New 4-Modulus Base---IEEE 2009.
	A VLSI Progressive Coding for Wavelet-based Image Compression---IEEE 2007.
	A New Low Power Test Pattern Generator Using a Variable-Length Ring Counter---IEEE 2009.
	A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations---IEEE 2009.
	FPGA Implementation of Viterbi Decoder---IEEE 200
	Asynchronous Computing in Sense Amplifier-based Pass Transistor Logic---IEEE 2008.
	A Low-Power Low-Area Multiplier Based on Shift-and-Add Architecture---IEEE 2009.
	Designing Efficient Online Testable Reversible Adders with New Reversible Gate---IEEE 2007.
	Deviation-Based LFSR Reseeding for Test-Data Compression---IEEE 2009.
	Hardware implementation of Variable Precision Multiplication on FPGA---IEEE 2009.
	Novel Area-Efficient FPGA Architectures for FIR Filtering With Symmetric Signal Extension---IEEE 2009.
	Power Optimization of Linear Feedback Shift Register (LFSR) for Low Power BIST---IEEE 2009.
	Spread Spectrum Image Watermarking with Digital Design---IEEE 2009.
	Superscalar Power Efficient Fast Fourier Transform FFT Architecture
	The Design and FPGA Implementation of GF (2128 ) Multiplier for Ghash---IEEE 2009.
	VLSI Design of Diminished-One Modulo 2n + 1 Adder Using Circular Carry Selection---IEEE 2009.
	Left to Right Serial Multiplier for Large Numbers on FPGA.
	A Compact AES Encryption Core on Xilinx FPGA.
	A Novel Multiplexer based truncated array multiplier.